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IDT74LVC16841A 3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in SSOP, TSSOP, and TVSOP packages
IDT74LVC16841A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
The LVC16841A low voltage 20-bit transparent latch is built using advanced dual metal CMOS technology. This high speed, low power latch is ideal for temporary storage of data. The LVC16841A can be used for implementing memory address latchs, I/O ports, and bus drivers. The output enable (OE) and latch enable (LE) controls are organized to operate each device as two 10-bit latches or one 20-bit latch. Flow through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The LVC16841A is ideally suited for driving high capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as a backplane drivers. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC16841A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
FUNCTIONAL BLOCK DIAGRAM
1OE
1
2OE
28
1LE
56
2LE
29
1D1
55
D C
2
2D1
42
D C
15
1Q1
2Q1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4602/1
IDT74LVC16841A 3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100
Unit V C mA mA mA
1OE 1Q1 1Q2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1LE 1D1 1D2
GND
1Q3 1Q4
GND
1D3 1D4
VCC
1Q5 1Q6 1Q7
VCC
1D5 1D6 1D7
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
GND
1Q8 1Q9 1Q10 2Q1 2Q2 2Q3
GND
1D8 1D9 1D10 2D1 2D2 2D3
NOTE: 1. As applicable to the device type.
PIN DESCRIPTION
Pin Names xDx xLE xOE xQx Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Description
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
VCC
2Q7 2Q8
VCC
2D7 2D8
GND
2Q9 2Q10 2OE
GND
2D9 2D10 2LE
FUNCTION TABLE(1)
Inputs xDx H L X X xLE H H L X xOE L L L H Outputs xQx H L Q(2) Z
SSOP/ TSSOP/ TVSOP TOP VIEW
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2. Output level before xLE HIGH-to-LOW transition.
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IDT74LVC16841A 3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74LVC16841A 3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Latch Outputs enabled Power Dissipation Capacitance per Latch Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical -- -- Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xDx to xQx (LE = HIGH) Propagation Delay xLE to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Set-up Time HIGH or LOW, xDx to xLE Hold Time HIGH or LOW, xDx to xLE xLE Pulse Width HIGH Output Skew(2) 2 2 4 -- -- -- -- -- 2 2 4 -- -- -- -- 500 ns ns ns ps 1 8 1.5 7 ns 1 9 1.5 8 ns 1 9 2 8 ns Min. 1 Max. 8 VCC = 3.3V 0.3V Min. 1.5 Max. 7 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC16841A 3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
6 2.7 1.5 300 300 50
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
LVC Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC Link
tPLH1
tPHL1
OUTPUT 1
VT
tSK (x)
tSK (x)
OUTPUT 2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVC16841A 3.3V CMOS LOW VOLTAGE 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
PV PA PF
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
841A 20-Bit Transparent Latch 16 Double-Density, 24mA
Blank No Bus-hold 74 -40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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